JCET Group Releases XDFOI Solutions Enabling Flexible Heterogeneous Integration


Key Highlights 

l  XDFOI™, a family of high-density fan-out packaging solutions, is an innovative wafer-level packaging technology designed to provide cost-effective solutions with high integration, high-density interconnection and high-reliability for the heterogeneous integration of chipsets, that are in high demand

l  Application scenarios includes FPGAs, CPUs, GPUs, AI and 5G, all of which require high integration and computing performance

l  Product validation and mass production are expected to be completed in 2H 2022


Shanghai, China, July 6, 2021 – JCET Group, a global leading provider of integrated circuit (IC) manufacturing and technology services, today announces the official launch of XDFOI™, an innovative solution for ultra-high-density fan-out packaging. This revolutionary technology will provide cost-effective solutions with high integration, high-density interconnection and high-reliability for the heterogeneous integration of chipsets, which are in high demand . This innovation from JCET Group will take its advanced chipset backend manufacturing to new heights. 

The XDFOI™ high-density fan-out package solution is a new silicon based, TSV-free, ultra-high-density wafer-level packaging technology with higher performance, higher reliability and lower cost compared to 2.5D TSV-based packaging technologies. XDFOI™ enables multiple redistribution layers (RDL) with line width and line spacing down to 2 micrometer. In addition, the extremely narrow bump pitch interconnect technology and large package size allow for the integration of multiple chips or chiplets, high bandwidth memories, and passive components.   

The XDFOI™ solution portfolio greatly reduces system cost and package size by integrating different functional devices in a system package with a wide range of applications. XDFOI™ primarily targets FPGA, CPU, GPU, AI and 5G applications, with demanding requirements for integration and computing performance to provide several functional chips (Chiplets) with Heterogeneous integration Package (HiP) solutions. 

Dr. Choon Heung Lee, CTO of JCET Group, said, "Moore's Law is slowing down, while the rapid development of information technology and the accelerated spread of digital transformation have stimulated a large number of diversified computing power needs. This market demand makes heterogeneous integration a new opportunity for advanced packaging technology, as it can effectively increase the IO density and computing performance within the chipset. JCET’s XDFOI™ solution will offer diverse options of heterogeneous integration for the customers’SoC as well as chiplets with unique technical advantages. Customer trials of the JCET XDFOI™ solution portfolio will begin soon and mass production is expected to begin in the 2nd half of 2022." 

Mr. Li Zheng, CEO of JCET Group, said, "JCET has been developing cutting edge technologies based on our rich technology accumulation and industry-leading R&D capability in both packaging and test. The launch of the XDFOI™ solution portfolio not only demonstrates our strong technology innovation capabilities, but also represents a crucial step towards our goal of enabling disruptive breakthroughs in advanced packaging technologies. JCET will continue its relentless pursuit of technology leadership and deepen its close synergy with the industry ecosystem to jointly contribute to the sustainable development of the IC industry."