Package-in-Package (PiP) is an innovative family of 3D packages that stack packaged chips and bare chips into one JEDEC standard FBGA. A pre-tested Internal Stacking Module (ISM) Land Grid Array (LGA) and a BGA or a Known/Probed Good Die (KGD) are stacked and interconnected with wire bonding, then molded into a CSP that is indistinguishable from a conventional FBGA package.
A typical PiP integrates ASIC logic with memory chip(s), can have a minimal 12x12mm footprint, 1.2 to 1.4mm maximum thickness, and incorporate a 0.5mm to 0.4mm ball pitch.
The PiP package can be assembled and board mounted like a conventional FBGA package and has equivalent package and board level reliability.
3D packaging is driven by wireless and consumer products that need package level functional integration in the smallest footprint, lowest profile and lowest cost CSP. Stacked die for Flash, SRAM and DRAM memories in a CSP are widely available today from memory suppliers but require KGD (especially for DRAM). As integration is extended to include complex and costly chips like ASIC in the same package with more Memory and Analog or RF chips, stacked packaging solutions are increasingly being utilized to maximize final test yield, expand supply chain and minimize the cost of ownership.
PiP enables new functionality in the shortest time-to-market and with minimum risk by stacking tested packages and known good logic or analog die sourced from the established supply chain. A lower PiP packaging cost, compared to the equivalent cost of separately packaged chips, and significantly reduced final test complexity both result in a module with lower cost of ownership.