Package-on-Package PoP

JCET’s Package-on-Package (PoP) family includes a stackable FBGA as the bottom PoP package (PoPb). PoPb is typically an ASIC or baseband device with land pads placed on the top periphery of the package surface to enable the stacking of a second FBGA or PoP top (PoPt) above. PoPt consists of memory or other silicon functionally assembled, tested and yielded independently. The two packages are combined by reflowing together (usually performed simultaneously) on the application board, to form PoP (Z-interconnection with solder ball). JCET offers the flexibility of stacking up to two devices in the PoPb and up to five devices in the PoPt.


As multi-die stacking becomes increasingly more common, known good die issues are critical for cost saving and throughput yield. For example, in a four die stack package, a single die can render the entire package unusable even if the other three die are fully functional. One way to overcome this problem is by using package stacking which can overcome known good die issues since die functionality can be checked after being packaged and before being placed on top of another known good package.

  PoP can provide an overall low profile as stacked and allows individual packages to be tested prior to stacking. This PoP approach is attractive to device manufacturers and end customers. Device manufacturers can focus on their core competencies and not worry about integrating other devices (test and yield implications) into the packages they sell. The end customer can leverage traditional sources for each device type and has more flexibility to configure devices as needed for a particular product and market.

• Stacking fully tested memory & logic packages eliminates known good die (KGD) issues
• Package-on-package stacking provides flexibility in mixing & matching IC technologies
• Devices can be procured from multiple mfg sources
• Meets accepted package & board level reliability standards for CSP
• CuOSP or Ni/Au on bottom pads of bottom PoP (PoPb) with lead free ball options
• Ni/Au on top memory interface pads of PoPb
• 0.4mm min. ball pitch on bottom / BGA pads & 0.65mm pitch on top memory interface pads of PoPb
• CuOSP or Ni/Au on bottom pad of top PoP (PoPt) with lead free ball options
• Top pin gate molding for PoPb (top center gate mold)
• Low stress and warpage die attach adhesives
• Low stress and warpage mold compound
• PoPb height less than 0.9mm (VFBGA-PoPb)
• PoPt height less than 1.0mm for 3 die stack (VFBGA-PoPt-SD3)
• PoPt height less than 1.2mm for 4 to 5 die stack (TFBGA-PoPt-SD5)
• Total package height dependent on PoPt configuration, but min. 1.4mm possible
• Full in-house electrical, thermal and mechanical simulation and measurement capability
• Full in-house package and substrate design capability

Test Services

• Product Engineering support
• Probe capability
• Program generation/conversion
• Drop Ship available

Additional Resource

PoP Datasheet

Bare Die fcPoP Datasheet

FiPoP Datasheet

Molded Laser fcPoP Datasheet

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