fcCuBE: Flip Chip Redefined

flip chip with Cu Pillar, BOL and Enhanced Processes (fcCuBE®)

A unique flip chip packaging technology that features Cu pillar bumps, Bond-on-Lead (BOL) interconnection and Enhanced assembly processes for a proven, low cost, high performance solution.


• Cu pillar with Pb-free cap enables ultra fine bump pitch for advanced silicon (Si) nodes (to ≤ 20nm), increased I/O density with superior thermal and electro-migration performance
• Patented, routing-efficient Bond on Lead (BOL) interconnection structure eliminates ELK /ULK damage on advanced Si nodes (40/28/20/16/14nm)
• BOL eliminates Solder-on-Pad (no-SOP) and allows relaxation of line / space design rules to offer lowest flip chip substrate cost
• BOL w/ Open Solder Resist (SR) relaxes substrate design rules while enabling dense and efficient routing
• Compatible with either JCET’s uniquely developed Mass Reflow (MR) process or Thermo-Compression Bonding (TCB)
• Lowest cost path to flip chip using Cu pillar: 10-30% cost reduction over standard flip chip packages for most designs

Low Cost Flip Chip Solutions

fcCuBE® is a patented technology pioneered by JCET nearly ten years ago that squarely addresses the requirements of performance, form factor and cost in the mobile, consumer and cloud computing markets. With a powerful combination of copper (Cu) pillar bumps, patented Bond-on-Lead (BOL) interconnection and enhanced assembly processes, fcCuBE technology delivers higher input/output (I/O) density and performance at a lower cost. The advantages of fcCuBE technology are driving wider customer adoption from cost sensitive markets such as mobile and consumer to networking and cloud computing where increased routing density and performance are imperative.

fcCuBE® technology’s unique BOL interconnect structure provides scalability to very fine bump pitches and high I/O while alleviating stress-related chip to package interaction (CPI), a common phenomenon associated with lead free and copper pillar bump structures. This is particularly important for mid to high-end networking and consumer applications.

Scalability, Reliability, High Performance

In conjunction with higher performance copper pillar interconnect, fcCuBE® technology leverages JCET’s patented, routing-efficient BOL interconnection structure to expand the scalability of flip chip technology to ultra fine bump pitches (to ≤ 40µm) and higher I/O densities and eliminates stress on delicate ELK/ULK structures at advanced silicon wafer nodes. BOL further enables substrate design rule simplification, elimination of tight Solder Resist Registration (SRR) rules, and elimination of Solder-on-Pad (SOP). This combination of enhancements results in a high performance, low cost solution which also allows greater design flexibility and a streamlined manufacturing process. fcCuBE’s robust interconnect structure effectively alleviates thermo-mechanical stress which is a common phenomenon in advancecd Si node ELK/ULK die with Cu Pillar bump.

MR and TCB Options

A unique feature of fcCuBE® technology is the inherent compatibility of the basic design with both standard Mass Reflow (MR) assembly or Thermo-Compression Bonding (TCB). JCET’s uniquely developed MR process, which utilizes either Mold Underfill (MUF) or Capillary Underfill (CUF), supports bump pitches down to 80um and below, providing customers a lower cost alternative to TCB at these pitches. TCB is utilized for more complex face-to-back or face-to-face bonding of processes necessitated by Through Silicon Via (TSV) technology. Reflow method is determined by Si node, pitch, I/O design and product time to market.


• In-house Cu pillar wafer bumping for 200 and 300mm wafers
• Ultra fine pitch capability: 
• 150µm to 40µm bump pitch
• 0.35mm minimum package ball (BGA) pitch in production
• MR process supports bump pitches down to 80µm and below
• Mold Underfill (MUF) further reduces package size and enables higher production throughput
• Non-conductive Paste (NCP) available for TCB
• Bumped wafer thinning: 100µm Si thickness in production, 75µm qualified
• Conventional 2/4 layer laminate, laminate build-up (BU) and ABF BU substrates
• Layer count reduction (6L to 4L, 4L to 2L) or 1-2-1 Build up to 4L PTH (2L with Low Cost BOM enables lowest cost flip chip solution)
• High Density (HD), and Ultra High Density (UHD) matrix strip for fcCSP and wide boat format for singulated FCBGA
• Broad fab node compatibility:
• 180n, 65n-LK, 40/28/20/14n-ELK/ULK
• Available in a wide range of package body sizes: 7x7mm to 35x35mm


fcCuBE® technology is a compelling solution for a wide cross section of end products in the low to high end mobile market, as well as mid to high end consumer and cloud computing markets:
• Mobile: 
application processors, baseband processors, PMIC, connectivity, RFIC, PA, touchscreen controllers, audio codec
• Consumer:
GPS, set top box chipsets, gaming consoles, GPUs, memory controllers, DTV, application processors, video processors, image/signal processors, CPU
• Cloud computing: 
ASIC, DSP, broadband processors, FPGA, ASSP, Ethernet processors, network storage, network switches


fcCuBE® technology is available across a wide range of platforms.
• FCBGA* is a singulated, exposed die package with CUF
• fcCSP* is an overmolded CSP package with MUF or CUF; available in ultra high density (UHD) and high density (HD) strip formats
• fcCSP-Hybrid is a fcCSP variation that features a "hybrid" stacked construction, i.e., flip chip die on bottom and wirebond die on top
• fcLGA is an exposed die product that does not have solder balls
• Bare Die fcPoP is a CSP package with CUF
• Molded Laser fcPoP is a Molded Laser chip scale package; also available in an exposed die configuration (PoP-MLP-ED)
• 3D TSV interconnect (Si-to-Si f-t-f / f-t-b bonding)
*Both FCBGA and fcCSP use solder balls for second level (BGA) interconnection

Additonal Resources
fcCuBE Datasheet

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