JCET offers Flip Chip on Leadframe (FCOL) package configurations, such as QFN and TSOT, with a full turnkey solution for FCOL from wafer bumping and assembly to final test. FCOL provides unique high current, high thermal performance in a cost effective chip scale package.
• Chip Scale Package Solution
Die to package clearance minimum to 75um per side. Die to package area ratio up to 90%.
• Excellent Electrical Performance
Standard round or round-oval mix copper pillar bump provides high current path (>1A with 100um CuP Bump) and lower Rdson as a result of direct die to leadframe connection.
• High Thermal Performance
Exposed die or metal lid attach significantly improves thermal dissipation through both top and bottom package surfaces, with up to ΘJC 80% reduction.
• Shorter Assembly Cycle Time
Simplified process could cut 3 days in standard assembly cycle time compared with WBQFN.
• Full Turnkey Service
JCET provides 200mm/300mm wafer bumping services in multiple manufacture sites, along with flip chip assembly and final tests.
Flip Chip Quad Flat No-lead Package
Flip Chip Thin Small Outline Transistor
Advantages• Routable Leadframe