Quad Flat No-Lead Packages QFN

JCET’s Quad Flat No-Lead (QFN) and Dual Flat No-Lead (DFN)package offering includes QFNs, QFNp, VQFN, WQFN, UQFN, XQFN, QFNp-dr and QFNs-mr. QFN is a leadframe based, plastic encapsulated chip scale package (CSP) that provides customers with an ideal choice for many applications where size, weight and thermal and electrical performance are important. A leadless package, QFN’s electrical connections are achieved by way of lands located on the bottom side of the component to the surface of the PCB. QFN packages have proven to be successful for a number of applications such as wireless handset, power management, analog baseband and Bluetooth devices.

JCET offers multiple QFN configurations in either punch or saw singulated formats. Punch singulated packages are individually “punched” from molded strips during final assembly; saw singulated packages are assembled in an array format and separated into individual components during the final sawing operation.

QFNp is a punched singulated package that features a thin, lightweight profile and excellent heat dissipation capability. QFNp offers a more compact, high performance and cost effective solution than conventional leadframe packages, particularly for mobile and handheld applications.

QFNp-dr is a punch singulated dual row package that features a significantly higher number of I/O terminal pads in a smaller footprint. The key to the increased performance capability of the QFNp-dr is in its leadframe design which features two rows of staggered I/O terminal pads with an exposed die pad for die grounding and improved thermal performance. The QFN saw singulated multi-row or QFNs-mr package is a saw singulated package in a land grid array (LGA) format with square or rectangular body sizes. By using a saw singulated manufacturing process, STATS ChipPAC can offer customers higher I/O count in a multi-tier format while retaining the same package size.

An exposed die pad coupled with extremely low RLC provides excellent electrical and thermal performance enhancements which are ideal for high frequency and high power applications, and are especially suited for wireless and handheld portable applications such as cell phones.

QFN-dr with staggered dual row leads offers higher I/O counts. JCET’s QFN packages are currently available in various body sizes and thicknesses, offered in standard and green/lead-free bill of materials and can be processed by conventional SMT equipment, benefiting surface mount operations downstream.


• Body sizes from 1.0mm x 1.3mm to 12mm x 12mm
• Pin counts from 4L to 156L
• Square or rectangular body size
• Leads on four sides of the body (QFN)
• Leads on two opposing sides of the body (DFN)
• Dual row lead design options
• Thin package thickness options
• Lead pitch: 0.40, 0.50, 0.65 and 0.80mm
• Custom lead/pitch configurations available
• Package profile heights: 0.45, 0.55, 0.75, 0.85 and 0.90mm
• Option for non-exposed die pad
• Available in gold or copper wirebond versions
• Multi-die versions available
• Chip on Lead (COL) using Wafer Backside Coating (WBC) available
• Thin packages per JEDEC available (V, W, U, X)
• Green materials set
• Option for 100% matte Sn or PPF
• Small chip scale design offers 50% reduction in board space (16L TSSOP vs. 16L QFN)
• 33% weight reduction (16L TSSOP vs. 16L QFN)
• Excellent thermal & electrical performance
• Full in-house package and leadframe design capability
• Full in-house assembly and test capability
• Full in-house electrical, thermal and mechanical simulation and measurement capability
• Wide range of open tool leadframe and die pad sizes available


• RF
• Power management
• Discretes
• Analog/Linear
• Logic
• Applications requiring enhanced electrical and thermal performance and reduced package size, thickness and weight

Additonal Resources
QFN Datasheet
QFNs-st Datasheet

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