JCET Announces Realization of 4nm Chip Packaging for Smart Phones


JCET Group (SSE: 600584), a leading global provider of Integrated Circuit (IC) backend manufacturing and technology services, recently announced that the company realized the packaging of 4nm chips for mobile phones, as well as the integrated packaging of CPU, GPU and RF chipset.

4nm is utmost advanced silicon node technology after 5nm and before 3nm and can be regard as a part of chiplet packaging introduction. As one of the products with cutting-edge technology products in IC industry, 4nm chips can be used in smartphones, 5G communications, Artificial Intelligence, autonomous driving, as well as GPUs, CPUs, Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs) ) and other products in the field of high-performance computing (HPC).

Under the continuous promotion of the market, electronic products are constantly developing towards miniaturization with multi-functionality. The size of chipset is getting smaller and the types of chipset are increasing, driving the demand for advanced packaging and testing technology going up. Advanced chipset such as 4nm chip require advanced packaging technology to ensure better system-level electrical and thermal performance.

At the same time, chipset packaging technology is also evolving towards multi-dimensional heterogeneous integration. Compared with the traditional chip stacking technology, multi-dimensional heterogeneous packaging realizes higher-dimensional chip packaging by introducing silicon interposer, redistribution layer interposer and their multi-dimensional combination. Another feature of this technology is the ability to optimally combine different densities of routing and interconnection to achieve an effective balance of performance and cost.

JCET’s XDFOI™ multi-dimensional advanced packaging technology is an innovative solution for ultra-high-density fan-out packaging solution, which provides cost-effective solutions with high integration, high-density interconnection and high-reliability for the heterogeneous integration of chipsets. It covers 2D, 2.5D and 3D integration technologies.

Moving into the future, based on its rich technological precipitation and global resources JCET will focus on innovation and industrialization of advanced packaging and testing technologies. Meanwhile, JCET will continue to deepen the collaboration with the industry ecosystem, and jointly contribute to the sustainable development of the IC industry.