JCET Chiplet Technologies Achieve High Volume Manufacturing


Jan 5, 2023, JCET Group, a leading global provider of Integrated Circuit (IC) backend manufacturing and technology services, announced that its XDFOI™ high-density multi-dimensional heterogeneous integration Chiplet technologies have entered the stage of high volume manufacturing (HVM) as planned, and the HVM of integrated packaging at 4nm chips for international customers have been achieved synchronously, with a maximum packaging area of about 1500mm².

With the rapid development of high-performance computing, AI, 5G, automobile, cloud, and other applications in recent years, continuous innovation of back-end manufacturing technologies is required to compensate for the slowdown of Moore's Law. In response to market demand, in July 2021 JCET launched the XDFOI™ high-density multidimensional heterogeneous integration technology platform covering 2D, 2.5D, and 3D Chiplet integration technologies.

Through continuous R&D and customer product verifications, JCET’s XDFOI™ continuously made breakthroughs. XDFOI™ places one or more logic chips (CPU/GPU, etc.), I/O chips, and/or high bandwidth memory chips (HBM) on the RDL Stack Interposer (RSI) to form a highly integrated heterogeneous package. XDFOI™ can "downsize" the high-density fcBGA substrate by transferring part of the distribution layers to the RSI substrate and using the advantages of the RSI with line width and line spacing down to 2 micrometers to reduce the chip interconnection spacing to achieve more efficient and flexible system integration. Additionally, some of the SoC interconnects can be transferred to the RSI, realizing the structural innovation based on the Chiplets and the high performance and low cost of chips.

At present, JCET’s XDFOI™ is capable of an RSI thickness down to 50μm, and a µBump pitch as low as 40μm, achieving high-density integration in a thinner and smaller area, and higher integration, higher module performance, and a smaller package footprint. At the same time, XDFOI™ enables metal deposition on the back of the package, which can effectively improve the heat dissipation efficiency, enhance the electromagnetic shielding capability of the package, and improve the yield of the chip products.

JCET’s XDFOI™ high-density multi-dimensional heterogeneous integration Chiplet technologies have already been used in high-performance computing, AI, 5G, automotive electronics, and other applications to help customers achieve smaller footprint products with faster transmission speeds and less power loss, meeting the growing demands of these end markets.